|By Maureen O'Gara||
|October 26, 2009 12:15 PM EDT||
Tilera, the start-up building high-performance multi-core processors that aren't x86, laid out a roadmap Monday that will see it sampling a single processor with a hundred RISC-based cores in the first quarter of 2011 and producing the widgets a few months later.
Imagine that, 100 cores.
The company believes the widget, called the TILE-Gx100, will be the world's first general-purpose 100-core processor and says it will be adopted by major service providers, potentially folks like Facebook and maybe Google - although Google's always the odd fish - for cloud infrastructure, dislocating the standard Intel-based cloud.
Tilera says the cloud is multi-core by nature but that it can deliver a "cloud in a rack" as opposed to an Intel "cloud in a container."
It says it's engaged with four of the five top IPS vendors and five of the top 10 UTM vendors while 10 universities are using Tilera as their multi-core teaching platform.
The part should also go into enterprise networking, multimedia and wireless infrastructures.
Quanta, the big Taiwan ODM, is working on some hush-hush cloud computing strategy and has just tucked $10 million into Tilera as part of the company's $25 million C round, bringing total investment to $64 million.
Tilera doesn't expect to be back to the trough ever again - it figures to break even in 2011 - and claims it hasn't a clue what Quanta means to do with widgetry. Could be an ODM thingie or a Quanta-branded something or other. Perhaps its intentions will become clear in the first half.
Anyway, Tilera hasn't been given to pre-announcing its widgetry, but since it's become the norm with its competitors, Cavium, RMI (now NetLogic), Intel and Freescale, Tilera figures it better be fashionable.
It's currently delivering its second-generation 32-bit TILEPro family, which has 32- and 64-cores, and its original 64-core TILE64 chips to 75 embedded customers. The gismos run SMP Linux 2.6.26, the LAMP stack, C, C++ and Java plus the ANSI C/C++ compiler, GNU tools, the Eclipse IDE and a hypervisor layer to virtualize hardware and I/O device drivers. It's got a Multicore Development Environment (MDE) for product deployment and promises easy programming.
The Gx will be a new 64-bit family that starts at 16 cores, tops out at 100 and has chips with 36 and 64 cores in between - mind you, each of the cores is 64-bit. The line will clock at a dialed-down 750MHz-800MHz up to 1.25GHz-1.5GHz and consume 10W-55W. The 36-core part will be first out of the gate - then the 16 - and start sampling around this time next year.
The company meant to go in graduated order, but, according to marketing director Robert Doud, customer demand pushed the schedule up.
Tilera claims the Gx100 will offer the highest performance of any processor yet announced, and that includes Intel's parts, by a factor of four. And it claims the Gx family raises the performance-per-watt bar by 10 times better compute efficiency than Intel's next-generation Westmere chip.
Doud quips that Tilera burns less power than the fans in a dual quad-core Nehalem machine.
Compared to its own Pro64 the Gx should be good for 4x the performance and twice the power density.
The Gx100 is supposed to do 4x the Nehalem-EX' eight cores in cloud computing; 4x Cavium's high-end 68xx Octeon II in deep packet inspection; and 30x TI's high-end multi-core DSP in wireless.
The company's two-dimensional iMesh interconnect makes an on-chip bus unnecessary and its Dynamic Distributed Cache system lets each core's local cache be shared coherently across the entire chip. That gives the Gx100 26MB of L3 cache for each core plus 32KB L1 I-cache, 32KB L1 D-cache and 256KB L2 cache for a total cache of 32GB for each chip.
Tilera claims the peer-to-peer distributed approach to cache scales and is superior to large shared memory that runs hot and creates performance bottlenecks.
Between the interconnect and the cache, the TILE architecture is supposed to scale nearly linearly with the number of cores on the chip, a feat that Tilera points out is "currently unmatched."
Tilera CEO Omid Tahernia figures boards using dozens of chips or more will be replace by one of his chips, simplifying system architecture, reducing cost, power consumption and PC board space.
Besides this consolidation, Tilera imagines its chips being used for granularity, allowing processing resources to be allocated to functions in precise 1% increments, and determinism, letting cores or clusters of cores be dedicated to specific tasks - or virtualized applications - including cache-coherent islands of compute for predictable performance.
It should translate into lower system costs, smaller footprints and quicker time-to-market using smaller development teams.
The Gx100 also has eight 10 Gbps ports that can become 32 1Gbps Ethernet ports and two 10-lane Interlaken chip-to-chip connections. It has four on-chip DDR3 DRAM controllers and will address 1TB of DRAM with 4Gbit RAMs.
Taiwan Semiconductor Manufacturing Company (TSMC), an early Tilera investor, will build the chips on its 40nm process. At this point Tilera has the physical layout and a simulator. It expects first silicon in 2H10.
Expected volume pricing will range from ~$400 for the Gx36 to ~$1,000 for the Gx100.
With its eye on the server market and its feet currently in the embedded market, Tilera has ported and optimized Memcached, the open source widgetry used to accelerate database-driven web sites, on its chips. It could turn up in 1U rack-mounted appliances. It'll get people associating Tilera with servers.
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